Low latency on chip communication based on hybrid NOC Architecture using X-Y router
Keywords:
Hybrid NOC architecture, x-y Routers, IP cores, mesh architectureAbstract
On-chip communication has two different type of architecture which can be classified as Bus and mesh based Networkson-Chip (NoC). Each of them has different features and applications. In this paper, we construct the hybrid architecture with using bus and mesh NOC architecture. In the hybrid architecture, heavy communication affinity IP cores are placed in the same subsystem. and this large mesh NoC get partitioned into several subsystems and one on one individual IPs, so that there is the reduction in the transmission latency of NoC . Efficient partition and mapping algorithm is proposed for reduction of the latency on the hybrid NOC architecture. It shows that an average latency improvement of 17.6% and more can be obtained when compared with the conventional mesh NoC architecture.
References
S. Bourduas and Z. Zilic, “A hybrid ring/mesh interconnect for networkon chip using hierarchical rings for global routing,” in International Symposium on Networkon-Chip, 2007, pp. 195–204.
H. M. Harmanani and R. Farah, “A method for efficient mapping and reliable routing for noc architectures with minimum bandwidth and area,” in IEEE Northeast Workshop on Circuits and Systems and TAISA Conference, June 2008, pp. 29–32.
W. Lee and G. E. Sobelman, “Mesh-star hybrid noc architecture with cdma switch,” in IEEE Proc. of International Symposium on Circuits and Systems, 2009, pp. 1349–1352.
T. D. Richardson, C. Nicopoulos, D. P. andV. Narayanan, Y. Xie, C. Das, and V. Degalahal, “A hybrid soc interconnect with dynamic tdma-based transaction-less buses and on-chip networks,” in Proc. of International Conference on VLSI Design, 2006.
Y. S. Cho, E. J. Choi, and K. R. Cho, “Modeling and analysis of the system bus latency on the soc platform,” in Proc. of International workshop on System-Level Interconnect Prediction, 2006, pp. 67–74.
J. D. Wang, “Low power mapping of cores onto hybrid noc architecture,” Master’s thesis, National Taiwan University, 2007.
W ijetunga, P., "High-performance crossbar design for system-on-chip," System-on-Chip for Real-Time Applications, 2003. Proceedings. The 3rd IEEE International Workshop on , vol., no.pp. 138- 143, 30 June-2 July 2003.
Pape, J; “Implementation of an On-chip Interconnect Using the i-SLIP Scheduling Algorithm: Intermediate Report – Specification and Timeline,” Nov 2006.
Mhamdi, L., Kachris, C., and Vassiliadis, S. 2006. A reconfigurable hardware based embedded scheduler for buffered crossbar switches. In Proceedings of the 2006 ACM/SIGDA 14th international Symposium on Field Programmable Gate Arrays (Monterey, California, USA, February 22 - 24, 2006). FPGA '06. ACM Press, New York, NY, 143-149.
Downloads
Published
How to Cite
Issue
Section
License
Copyright (c) 2014 COMPUSOFT: An International Journal of Advanced Computer Technology
This work is licensed under a Creative Commons Attribution 4.0 International License.
©2023. COMPUSOFT: AN INTERNATIONAL OF ADVANCED COMPUTER TECHNOLOGY by COMPUSOFT PUBLICATION is licensed under a Creative Commons Attribution 4.0 International License. Based on a work at COMPUSOFT: AN INTERNATIONAL OF ADVANCED COMPUTER TECHNOLOGY. Permissions beyond the scope of this license may be available at Creative Commons Attribution 4.0 International Public License.
