Vhdl Implementation and Comparison of Complex Multiplier Using Booth’s and Vedic Algorithm
Keywords:
Vhdl, COMPLEX MULTIPLIER, Booth‟s algorithmAbstract
For designing of complex number multiplier basic idea is adopted from designing of multiplier. An ancient Indian mathematics " Vedas" is used for designing the multiplier unit. There are 16 sutra in Vedas, from that the Urdhva Tiryakbhyam sutra (method) was selected for implementation complex multiplication and basically Urdhva Tiryakbhyam sutra applicable to all cases of multiplication. Any multi-bit multiplication can be reduced down to single bit multiplication and addition by using Urdhva Tiryakbhyam sutra is performed by vertically and crosswis e. The partial products and sums are generated in single step which reduces the carry propagation from LSB to MSB by using these formulas. In this paper simulation result for 4bit complex no. multiplication using Booth‟s algorithm and using Vedic sutra are illustrated. The implementation of the Vedic mathematics and their application to the complex multiplier was checked parameter like propagation delay.
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