Area Optimized Advanced Encryption Standard


  • Aher SR Dept. of Electronics and Telecommunication Engineering SPCOE, Otur, University of Pune Pune, Maharashtra, India
  • Kharat GU Dept. of Electronics and Telecommunication Engineering SPCOE, Otur, University of Pune Pune, Maharashtra, India


EDK, Real time Communication, AES, Security, XPS, EDKRTOS


Performance evaluation of the Advanced Encryption Standard candidates has become led to intensive study of both hardware and software implementations. However, number of papers presents various implementation results, it shows that efficiency could still be greatly improved by applying effective design rules adapted to devices and algorithms. This paper shows various approaches for efficient FPGA implementations of the Advanced Encryption Standard algorithm. For different applications of the AES algorithm may require different s peed/area tradeoffs, we propose a vital study of the possible implementation schemes, but also the discussion of design methodology and algorithmic optimization in order to improve previous reported results. We propose system to evaluate hardware efficiency at different steps of the design process. We also use an optimal pipeline that takes the place and route constraints into account. Resulting circuits significantly improve the previous reported results: throughput has been up to 18.5 Gbits/sec and the area requirements can be limited to 542 slices and 10 RAM blocks with a ratio throughput/area improved by minimum 25% of the best-known designs in the Xilinx Virtex- E technology.


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How to Cite

Aher, S. R., & Kharat, G. U. (2024). Area Optimized Advanced Encryption Standard. COMPUSOFT: An International Journal of Advanced Computer Technology, 3(08), 1059–1064. Retrieved from



Original Research Article

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