Area Optimized Advanced Encryption Standard

Authors

  • Aher SR Dept. of Electronics and Telecommunication Engineering SPCOE, Otur, University of Pune Pune, Maharashtra, India
  • Kharat GU Dept. of Electronics and Telecommunication Engineering SPCOE, Otur, University of Pune Pune, Maharashtra, India

Keywords:

EDK, Real time Communication, AES, Security, XPS, EDKRTOS

Abstract

Performance evaluation of the Advanced Encryption Standard candidates has become led to intensive study of both hardware and software implementations. However, number of papers presents various implementation results, it shows that efficiency could still be greatly improved by applying effective design rules adapted to devices and algorithms. This paper shows various approaches for efficient FPGA implementations of the Advanced Encryption Standard algorithm. For different applications of the AES algorithm may require different s peed/area tradeoffs, we propose a vital study of the possible implementation schemes, but also the discussion of design methodology and algorithmic optimization in order to improve previous reported results. We propose system to evaluate hardware efficiency at different steps of the design process. We also use an optimal pipeline that takes the place and route constraints into account. Resulting circuits significantly improve the previous reported results: throughput has been up to 18.5 Gbits/sec and the area requirements can be limited to 542 slices and 10 RAM blocks with a ratio throughput/area improved by minimum 25% of the best-known designs in the Xilinx Virtex- E technology.

References

AI-WEN LUO, QING-MING YI, MIN SHI“Design and Implementation of Area-optimized AES Based on FPGA” Published by 2011 International Conference on Business Management and Electronic Information.

Ahmed, S.; Samsudin, K.; Ramli, A.R.; Rokhani, F.Z. “Effective implementation of AESXTS on FPGA” Published in TENCON 2011 -2011 IEEE Region 10 Conference.

Kuo-Huang Chang1, Yi-Cheng Chen2, ChungCheng Hsieh1, Chi-Wu Huang2 and Chi-Jeng Chang1 “Embedded a low area 32-bit AES for

image encryption/decryption application” Published by IEEE International Symposium on Circuits and Systems, 2009. ISCAS 2009

Shanxin Qu; GuochuShou; Yihong Hu; ZhigangGuo; Zongjue Qian “High Throughput, Pipelined Implementation of AES on FPGA”Published in International Symposium on Information Engineering and Electronic Commerce, 2009. IEEC '09.

Kaur, Swinder; Vig, Renu, “Efficient Implementation of AES Algorithm in FPGA Device”Published in International Conference on Conference on Computational Intelligence and Multimedia Applications 2007.

Helion Technologies Ltd, “Fast AES XTS/CBC Core for Xilinx FPGA” – (XEX-based Tweaked Codebook with Ciphertext Stealing), IP Core,http://www.heliontech.com/aes_xex.htm.

Hatzidimitriou, E.; Kakarountas, A.P.; ,"Implementation of a P1619 crypto-core for Shared Storage Media," MELECON 15thIEEE Mediterranean Electrotechnical Conference , vol., no., pp.597-601,

M. Dworkin, Recommendation for Block Cipher Modes of Operation: The XTS-AES Mode for Confidentiality on Storage Devices, NIST

Special Publication 800-38E, US Nat’l Inst. of Standards and Technology, http://csrc.nist.gov/publications/nistpubs/80038E/nist-p-800-38E.pdf.

Martin, L.; "XTS: A Mode of AES for Encrypting Hard Disks," Security & Privacy, IEEE, vol.8, no.3, pp.68-69.

Downloads

Published

2024-02-26

How to Cite

Aher, S. R., & Kharat, G. U. (2024). Area Optimized Advanced Encryption Standard. COMPUSOFT: An International Journal of Advanced Computer Technology, 3(08), 1059–1064. Retrieved from https://ijact.in/index.php/j/article/view/186

Issue

Section

Original Research Article

Similar Articles

<< < 17 18 19 20 21 22 23 24 25 26 > >> 

You may also start an advanced similarity search for this article.